In the field of semiconductor manufacture, it is required to form a highly fine wiring pattern to meet a recent trend for miniaturization of semiconductor devices. To form this highly fine wiring pattern, an etching processing having high selectivity needs to be performed. Patent Document 1 describes a technique regarding an etching method. In the etching method described in Patent Document 1, a mixed gas of a CH3F gas and an O2 gas is used as an etching gas for etching a silicon nitride film covering a silicon oxide film, and a mixing ratio (O2/CH3F) of the O2 gas to the CH3F gas in the mixed gas is set to be in the range from 4 to 9. Patent Document 2 describes a technique regarding an etching method of forming a spacer having multiple films. In the etching method disclosed in Patent Document 2, there is performed a multi-stage processing in which anisotropic etching is first performed on a low-k material having high selectivity with respect to silicon nitride and isotropic etching is then performed on SiN having high selectivity with respect to the low-k material. Further, Patent Document 3 discloses a technique of forming a thin film using atomic layer deposition (ALD) or chemical vapor deposition (CVD).
Patent Document 1: Japanese Patent Laid-open Publication No. 2003-229418
Patent Document 2: Japanese Patent Laid-open Publication No. 2015-159284
Patent Document 3: US Patent Application Publication No. 2016/0163556
Patent Document 4: Japanese Patent Laid-open Publication No. 2012-505530